AMD plan to manipulate processor cache memory in order to expand their range and reduce the production costs of its chips. These, reported, changes will also affect the upcoming Athlon64 chip. This news story could be described as "the story AMD tried to ban," as the French web site that first published it, X86-secret.com, were forced to remove it.
The Athlon64 is expected to launch with performance ratings of 3400+ and 3100+ in September, ratings which will jump to 3700+ in Q4 of 2003. Q4 of 2004 will find the Athlon64 sporting a 4300+ rating.
The introduction of the new Athlon chip will also influence the company's future plans for its existing Athlon XP line.
The changes will aim to streamline the production process and help the company optimize the use of its factory space while significantly reducing production costs.
At the core of the AMD plan lies the processor's memory cache. The cache is memory located on the chip that sppeds up processor performance by providing fast access to data.
The Athlon64 3700+, 3400+ and 3100+ chips will initially come with 1MB of such cache memory. According to AMD's plans however, in Q4 the clock speed will substantially increase, while at the same time the cache will be reduced to 256KB.
The idea behind the plan is simple, decrease the amount of cache, compensate by increasing clock speed and you can shrink the size of the chip keeping performance constant. Smaller chips means cheaper more competitive and profit making ones.
Plans for the current Athlon XP range are slightly different. The new, recently confirmed, Thornton core will feature a partially active cache which will keep the chip to the same size as the current, top-of-the-line XP, the Barton 3200+ carrying 512KB of cache. This would mean that all new XP's would be made from the same wafer, greatly streamlining the manufacture process. Another advantage would be that AMD could market Bartons produced with one cache segment damaged, as Thorntons.
Simple on paper, the process will be very tricky to pull-off in practice. Although cache changes are commonplace and have been used extensively, both by Intel and AMD in order to seperate their budget range from the high-end chips, this particular plan will face a variety of problems.
Kevin Krewell, senior editor of the Microprocessor Report wrote Not all applications respond in the same way. Some applications are more sensitive to cache size and some to clock frequency. AMD have their work cut out for them, work this out technically and then convince users that a chip carrying 1/4 the cache of another can perform just as well.
Although AMD have refused to comment, the have been confirmed by a wide variety of industry experts.
